Presently, the highest performance computer systems are the vector processors which are mainly employed for technical and scientific applications. However, the performance potential of the pipelined functional units of a vector processor can only efficiently be used if the required data transfer between main memory and the CPU, respectively the CPUs in case of multiprocessor systems, can optimally be routed. This research investigates the access to main memory of a vector processorsystem (single processor System as well as multiprocessor systems with shared memory) with the aid of analytic models, measurements on a double processor System CRAY X-MP and simulations. The emphasis of the investigations is put on lang sequences of accesses to m...
In this paper, we use execution-driven simulation to study and compare vector processing performance...
SIGLECNRS 14802 E / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc
When accessing streams in vector multiprocessor machines, degradation in the interconnection network...
Most existing analytical models for memory interference generally assume random bank selection for e...
The high latency of memory accesses is one of the factors that most contribute to reduce the perform...
An innovative cache design for vector computers, called a prime-mapped cache, is introduced. By util...
The purpose of this paper is to show that multi-threading techniques can be applied to a vector proc...
This paper presents an experimental study on cache memory designs for vector computers. We use an ex...
The performance of a vector processor accessing vectors is strongly dependent on the conflicts produ...
The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnectio...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
In this paper we present the results of a detailed simulation study of the execution of vector progr...
The Vector Processor is a Single-Instruction Multiple-Data (SIMD) parallel processing system based o...
This paper presents mathematical foundations for the design of a memory controller subcomponent that...
Today, the field of high-speed computers and supercomputing applications is dominated by the vector-...
In this paper, we use execution-driven simulation to study and compare vector processing performance...
SIGLECNRS 14802 E / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc
When accessing streams in vector multiprocessor machines, degradation in the interconnection network...
Most existing analytical models for memory interference generally assume random bank selection for e...
The high latency of memory accesses is one of the factors that most contribute to reduce the perform...
An innovative cache design for vector computers, called a prime-mapped cache, is introduced. By util...
The purpose of this paper is to show that multi-threading techniques can be applied to a vector proc...
This paper presents an experimental study on cache memory designs for vector computers. We use an ex...
The performance of a vector processor accessing vectors is strongly dependent on the conflicts produ...
The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnectio...
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By...
In this paper we present the results of a detailed simulation study of the execution of vector progr...
The Vector Processor is a Single-Instruction Multiple-Data (SIMD) parallel processing system based o...
This paper presents mathematical foundations for the design of a memory controller subcomponent that...
Today, the field of high-speed computers and supercomputing applications is dominated by the vector-...
In this paper, we use execution-driven simulation to study and compare vector processing performance...
SIGLECNRS 14802 E / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc
When accessing streams in vector multiprocessor machines, degradation in the interconnection network...