A 500MS/s Flash-ADC with Selectable Power Consumption

[[abstract]]本篇論文提出一快閃式類比數位轉換器，可提供使用者選擇六種不同的功率消耗，藉由輸入六種不同偏壓而得之。本篇論文使用傳統式Flash-ADC作為設計架構，對於比較器的部分，輸入六種不同的偏壓，將會得到六種不同的解析度與功率消耗。取樣頻率在500MHz，供應電壓為1.8V，使用Hspice及TSMC 0.18μm CMOS製程進行模擬，當比較器輸入偏壓為0.85V、0.9V及1.0V時ENOB皆為5以上，功率消耗分別為26.6mW、22.5mW與14.5mW；輸入偏壓為1.1V、1.15V、1.2V時ENOB皆為4以上，功率消耗分別為8.8mW、6.58mW及5.06mW。此外也針對三組不同的取樣頻率進行模擬，分別為400MHz、250MHz及200MHz，個別對應到輸入偏壓為0.9V、1.0V及1.1V時ENOB皆為5以上。[[abstract]]In this paper, a 500M sample/s Flash-ADC is presented which can select 6 different power consumption from 6 different input Vbias. In comparator, we have 6 different input Vbias to obtain 6 different resolution and power consumption. In this study, we use TSMC 0.18μm CMOS technology and 1.8V power supply to simulate the Flash-ADC. When sample rate is 500MHz and input Vbias are 0.85V, 0.9V, 1.0V, 1.1V, 1.15V and 1.2V, the corresponding ENOB are 5.49, 5.46, 5.28, 4.78, 4.45 and 4.22, and the power consumption are 26.6mW, 22mW, 14.5mW, 4.78mW, 8.8mW, 6.58mW and 5.06mW respectively. The simulation results show that the sample rate and Vbias are 400MHz with 0.9V, 250MHz with 1.0V and 200MHz with 1.1V, the ENOB are 5.54, 5.55 and 5.78, and the power consumption are 22.3mW, 14.0mW and 8.1mW