A Low-Power Efficient Direct Digital Frequency Synthesizer Based on New Two-Level Lookup Table

[[abstract]]This workpresents a low power direct digitalfrequency synthesizer (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide ROM lookup table into two parts. The ROM size of the proposed architecture is 25% less than that of conventional two-level table. The hardware complexity of the new DDFS architecture compared to the traditional two-level table DDFS can be omitted one multiplier. A synthesized 0.35-pm DDFS with a SFDR of - 80dB, runs up to 100MHz and consumes 81-mW at 3.0v. The power efficiency is 0.81-m W/MHz, which represents an enhancement of more than 38% compared to the conventional DDFS