[[alternative]]Chip Design and Implementation of CMOS Mixers for WCDMA and UWB Applications

碩士電機工程學系[[abstract]]在本論文中所設計的混波器分別操作在寬帶分碼多工存取(WCDMA)的發射機與超寬頻系統(UWB)的接收機。利用電流再生(Current-Reuse)與多閘極電晶體(MGTR)的方式設計一個2GHz的CMOS直轉式的混波器應用在WCDMA發射機，混波器中的差動輸入轉導級使用電流再使用的架構來克服供應電壓的限制並且使用多閘極相連的電晶體的方式來增加第三階截斷點的線性度。並利用差動轉單端的電路將差動的RF訊號轉換成單端。此混波器利用UMC 0.18微米製程所設計與製作，當輸入中頻10MHz的頻率和-30 dBm的功率與輸入1.94GHz本地振盪的訊號和0dBm的功率與輸出1.95GHz的RF訊號，在1伏特的供應電壓下，此晶片可達到：5.75dB的轉換增益、10dBm的第三輸出階截斷點、6.2dBm的第三階輸入截斷點和5.35毫瓦的功率消耗。 另一個全整合3 ~ 5 GHz的混波器被設計應用在超寬頻系統。此混波器的設計採用動態注入的電路來消除雜訊，為了要調整轉換增益、線性度和雜訊指數，我們在NMOS電晶體的閘極和汲極間串聯一個電容和一個電阻。應用於3 ~ 5 GHz的單端訊號轉換成差動訊號的主動平衡器也整合在晶片中。3到5GHz、功率-30dBm輸入的RF與功率0dBm輸入的本地振盪訊號，在1.8V的供應電壓下，此晶片量測可達到5.2 ~ 8.8dB的轉換增益、-2.5 ~ 3.7dBm的第三階輸入截斷點和-11 ~ -7.8dBm的1dB壓縮點。[[abstract]]In this thesis, the designed mixers are operated individually in WCDMA transmitter and UWB receiver. A 2GHz CMOS direct-conversion mixer with current-reuse and multiple-gated-transistors (MGTR) topologies is designed for application in a WCDMA transmitter. The current-reuse topology is used to overcome the limitation of supply voltage and the MGTR topology is used to increase the linearity of third-order intercept point in the differential input transconductance stage of the mixer. The differential RF signal is converted into single-end signal by a differential-to-single circuit. The mixer is designed and implemented in UMC 0.18 μm CMOS technology. With -30 dBm power for 10 MHz input IF, 0 dBm power for 1.94 GHz input LO and 1.95 GHz output RF, the test chip achieved: 5.75 dB conversion gain, 10 dBm OIP3, 6.2 dBm IIP3, and 5.35 mW power consumption for 1 V supply voltage. Another fully integrated 3 to 5 GHz CMOS mixer is also designed for UWB system. The designed mixer utilizes a dynamic injection circuit to reduce noise figure. In order to adjust the conversion gain, linearity, and noise figure easily, we connect a capacitor and a resistor in series between the drain and the gate of a NMOS transistor. An active balun which converts the single-ended input signals to differential signals for 3 to 5 GHz is also integrated in the chip. With -30 dBm for 3 to 5 GHz input RF and 0 dBm for 3 to 5 GHz input LO, the measured chip achieved 5.2 ~ 8.8 dB conversion gain, -2.5 ~ 3.7 dBm IIP3 and -11 ~ -7.8 dBm P1dB for 1.8 V supply voltage