[[alternative]]A PLL Based COMS Frequency Synthesizer for Low-Power WCDMA Applications

碩士電機工程學系[[abstract]]本論文主要為提出一個適用於2 GHz頻帶WCDMA之低功率CMOS頻率合成器。所設計的頻率合成器是以台積電的0.18微米1P6M的製程為載具進行模擬和線路的實現。在本論文中，我們提出一個設計鎖相迴路(PLL)的模擬模型，此模型的模擬速度相當快速。在此頻率合成器中所設計的電感-電容電壓控制振盪器(LC-tank VCO)，我們使用穩定的互補式交互耦合電晶體對的架構，因為此種架構可以達到低相雜訊和低溫度變化所造成的頻率飄移。經由模擬，此電感-電容電壓控制振盪器(LC-VCO)的相位雜訊，在1 MHz的偏移頻率下為-115 dBc/Hz，振盪頻率的範圍可以從4.2 GHz到4.35 GHz，調諧範圍大約可以達到19.33%。在此頻率合成器中的相位頻率合成器(PFD)，採用改進之後的nc-type和percharge-type並行使用的架構，而且伴隨著一個鎖定偵測器。在設計充電浦(CP)的部分，採用電流控制的架構，此種架構可以有效的減少動態功率消耗，而且可以產生一個穩定的控制電壓給電壓控制振盪器做調頻的控制。在除頻器的部分，我們使用一個雙模組的預除器和一個pulse-swallow的除頻器去組成一個完整的除頻器。此頻率合成器，在1.8伏特的操作電壓下，僅消耗19.6毫瓦的功率消耗，鎖定時間為160微秒，所以這個合成器是可以適用於WCDMA接收器。而整個頻率合成器在晶片中所佔的面積約為1.18 x 1.23 mm2。[[abstract]]This thesis presents a 1.8 V 2GHz band low-power CMOS frequency synthesizer designed in TSMC 0.18μm 1P6M RF/Mixed-Signal CMOS process that meets the WCDMA specifications. In that, we propose a fast simulation model for the design of PLL. We employ a stable complementary cross-coupled transistor pair LC-tank VCO in designing the frequency synthesizer which achieves low phase noise and low temperature-variation drift. The simulated phase noise of the proposed LC-VCO is -115dBc/Hz at 1MHz offset. The oscillating frequency is ranging from 4.2 GHz to 4.35GHz. The tuning range of the proposed LC-VCO is about 19.33%. The PFD of the frequency synthesizer is used to modify a nc-type and a precharge-type architecture with a locked detector. The designed charge pump used current-steering structure can reduce dynamic power consumption and generate stable voltage to adjust the VCO frequency. We employ a dual modulus prescaler and a pulse-swallow frequency divider to form the complete frequency divider. This frequency synthesizer consumed 19.6 mW with 1.8 V supply voltage and 160 μs locked time that is suitable to be used in WCDMA receiver. The overall frequency synthesizer occupies a chip area of 1.18 x 1.23 mm2