[[alternative]]Chip Design of Direct Level-Signal Transition Based Analog-to-Digital and Digital-to-Analog Converters

碩士積體電路設計研究所[[abstract]]許多具多級處理架構的類比數位轉換器(ADC)架構中都存在著一個數位類比轉換器(DAC)，但是數位類比轉換器(DAC)本身就有著非理想效應的存在，並且在轉換的過程中發生訊號誤差。本論文利用一多階層訊號轉換技術來取代傳統數位類比轉換器(DAC)，不僅可減少電晶體的使用數量，更可降低功率消耗，並且減少訊號的誤差。 本論文提出一個十二位元，利用一多階層訊號轉換技術，以及100MHz 取樣頻率的類比數位轉換器(ADC)，此系統的主要電路包含取樣保持電路、快閃式類比數位轉換器(ADC)、多階層訊號轉換電路、減法器、增益級、時脈產生器、暫存器等電路。 本論文的類比數位轉換器(ADC)與數位類比轉換器(DAC)使用0.18um 1P6M CMOS製程技術以及使用Hspice模擬，類比數位轉換器系統在 100MHz的取樣頻率下，輸入範圍為0~1.8V，而電源供應為1.8V時，整體電路的消耗功率為43mW。根據模擬結果，在100MHz的取樣頻率下，微分非線性誤差在0.5LSB以內，積分非線性誤差在±±0.73LSB以內。數位類比轉換器系統在1GHz的取樣頻率下，輸入範圍為0~1.8V，而電源供應為1.8V時，整體電路的消耗功率為12 mW。根據模擬結果，在1GHz的取樣頻率下，微分非線性誤差在0.34LSB以內，積分非線性誤差在±0.42 LSB以內。[[abstract]]Many analog-to-digital converters with multi-stage processing constructions all include a digital-to-analog converter (DAC) in each stage. But digital-to-analog converter itself exist a non-ideal effect, and can have signal error in the conversion procedure. In this thesis, we proposed a direct level-signal transition technique to replace the traditional digital-to-analog converter. The proposed technique reduces the transistor numbers and thus can expect to have lower power consumption and signal errors. In this thesis, we proposed the design of a 12-bit 100 MHz sample-rate A/D converter, implemented with direct level-signal transition technique. The architecture consists of the following major blocks, i.e., a sample-and-hold circuit, a flash A/D converter, a direct level-signal transition circuit, a substractor, a gain amplifier, a clock generator, and a shift/register. The A/D converter and D/A converter have been implemented in TSMC 1P6M 0.18μm CMOS technology and simulated by Hspice. The ADC conversion time of one sampled period is 100MHz with 1.8V reference voltage range. The obtained power consumption is 43mW with 1.8V supply voltage. The measured differential non-linearity (DNL) error and integral non-linearity (INL) error are ±0.5 LSB and ±0.73 LSB, respectively. The DAC conversion time of one sampled period is 1GHz with 1.8V reference voltage range. The obtained power consumption is 12mW with 1.8V supply voltage. The measured differential non-linearity (DNL) error and integral non-linearity (INL) error are ±0.34 LSB and ±0.42 LSB, respectively