[[alternative]]Research of the Direct Digital Frequency Synthesizer

碩士積體電路設計研究所[[abstract]]本論文提出利用三角和公式實現ROM-Less直接數位式頻率合成器（DDFS），利用動態回傳修正電路來降低誤差量。本文直接數位式頻率合成器的架構包含2個加法器、2個乘法器以及1個動態修正電路來產生完整的正交輸出，所以此架構可以有效的降低晶片所佔用面積、功率消耗以及生產所需的成本。 本文使用Matlab模擬此架構的最大誤差量約為0.0146，與無雜訊動態範圍(SFDR)大約在100db及最高的操作頻率約為50MHz。目前本架構與傳統的直接數位式頻率合成器相比較，其誤差量改善了大約27.4％。 關鍵詞：直接式數位頻率合成器、頻率合成、查表法、頻率控制字元。[[abstract]]This paper proposed that realizes ROM-less direct digital frequency synthesizer (DDFS) to utilize based on trigonometric formula, and using dynamic feedback circuit to reduce the errors. This proposed DDFS consists of two adders、two multipliers and dynamic correction circuit to generation quadrature outputs, so it can effective reduce the occupied chip area, the power consume and the cost. The present paper simulation results maximum of errors is about 0.0146 by using Matlab, and Spurious Free Dynamic Range (SFDR) is about 100db, the maximum clock frequency around at 50MHz. Now architecture with conventions of direct digital frequency synthesizer to compare, the errors to improve is about 27.4%