[[alternative]]Chip Design of High Performance Voltage-Controlled Oscillators

碩士積體電路設計研究所[[abstract]]在本論文中，一共設計了三種電壓控制振盪器晶片，各操作於不同的頻段，皆以TSMC 0.18μm CMOS製程元件model為基礎來進行電路設計。 我們所設計的第一個電路，是利用互補式交連耦合架構來提供使LC-tank振盪所須的負電阻，並且使用switched-capacitor技術使得此VCO可以有3.16~4.94GHz約1.7GHz的寬頻調變範圍，消耗功率為9.4mW，但此電路下線晶片的量測結果無法正常動作，本人會在論文中提出檢討。 第二個電路是以current-reuse架構為基礎來設計24GHz振盪頻率之VCO，並加入了雜訊濾波器來降低電路之相位雜訊，此電路在24GHz振盪頻率時的相位雜訊在1 MHz偏移頻率下為-108.9dBc/Hz，消耗功率為8.2mW，可調頻率範圍為23~25.7GHz. 第三個電路為一差動考畢茲架構之VCO，具有考畢茲架構所具有之低相位雜訊特性，並且也較傳統考畢茲架構之消耗功率低。此電路之振盪中心頻率為20GHz，中心頻率之相位1MHz偏移頻率下為-113dBc/Hz，消耗功率為5.72mW，可調頻率範圍為19.5~20.6GHz.此電路所達到之FOM值為-191.4.[[abstract]]In this thesis, we designed three VCO chips that are operating at various oscillation frequencies. All the circuit designs are based on TSMC 0.18μm CMOS standard technology model. The first designed circuit using a complementary cross-coupled architecture to provide negative resistance for sustaining oscillation of LC-tank and switched-capacitor topology array to let the VCO can be tuned between 3.16 to 4.94GHz with 9.4mW power consumption. The second designed circuit is a 24GHz VCO based on current-reuse architecture. A noise filter is introduced in the VCO to enhance the phase noise performance of VCO. The simulated phase noise is -108dBc/Hz at 1MHz offset away from the oscillation frequency of 24GHz. The VCO-core power consumption is 8.2mW. The frequency can be tuned between 23~25.7GHz. The third designed circuit is a 20GHz differential colpitts VCO, this architecture take the advantage on low phase noise of conventional colpitts VCO, and consume lower power compared to the conventional single-ended colpitts VCOs. We removed the two current sources and replaced by inductors because the current source will contribute extra noise. The simulated phase noise is -113dBc/Hz at 1MHz offset from the carrier frequency of 20GHz, the VCO-core power consumption is 5.72mW and the frequency can be tuned between 19.5~20.6GHz. The FOM of this VCO can achieve -191.4