[[alternative]]Chip Design of Source and Gate Output Buffers for TFT-LCD Driver Applications

碩士積體電路設計研究所[[abstract]]本論文的目標在於薄膜電晶體平面液晶顯示器(TFT-LCD)之驅動晶片設計。TFT-LCD驅動電路有兩種：源極驅動器和閘極驅動器。首先，提出一個應用在源極驅動器的輸出緩衝器或數位類比轉換器之參考電壓電路，利用大小相同的N型電晶體和P型電晶體的閘-源極電壓，因為受溫度影響的切入電壓和遷移率已被互補抵消，所以獲得不隨溫度變化的穩定輸出電壓，在溫度範圍-70℃~150℃時的溫度係數小於0.68 ppm/℃。 第二部份，提出一個應用在高解析度TFT-LCD源極驅動器的高迴轉率、低功率與低抵補電壓之高驅動能力CMOS之軌對軌輸出類比緩衝器，具有互補式疊接差動輸入對，及共源極推拉輸出端和輔助電晶體的架構，擁有低功率、高驅動能力的效能；在3.3 V的操作電壓，驅動1 nF的大電容時，上升與下降迴轉率可達到20 V/μs和18 V/μs，靜態電流為1 μA，抵補電壓為2.5 mV。 第三部份，我們提出一個驅動高負載的TFT-LCD閘極驅動器之全擺幅輸出數位緩衝器，利用互捕式雙提升技術(CDUB)來提升驅動能力，模擬結果顯示在驅動TFT-LCD UXGA規格的掃瞄線面板下，在操作電壓5 V時的延遲時間皆小於2.8 μs，功率消耗只有0.74 mW。[[abstract]]In this thesis, we focus on the design of driver circuits for TFT-LCD display. The driver circuits of TFT-LCD are composed of two parts, the source driver and the gate driver. First, we propose a CMOS voltage reference circuit, which is designed for CMOS output buffer or DAC of TFT-LCD source drivers. The temperature-stable voltage reference is based on the same magnitude of gate-source voltage of NMOS and PMOS transistors that provides the temperature-compensation mechanism for the variations of threshold voltage and mobility. It gives a temperature coefficient of less than 0.68 ppm/℃ from -70℃ to 150℃. Second, we propose a high driving capability CMOS rail-to-rail output analog buffer with high slew-rate, low power and low offset voltage for high resolution TFT-LCD source drivers. Low power and high driving capability are achieved by using a telescope-cascode based complementary differential input stage combing with a common source push-pull stage and two auxiliary driving transistors. The output buffer attained 20 V/μs and 18 V/μs rising/falling slew-rates, 1 μA static current, and 2.5 mV offset voltage for 1 nF load capacitance with a power supply of 3.3 V. Third, we propose a high-speed full-swing output digital driver for heavy-loads TFT-LCD gate drivers. High driving capability is achieved by using a Complementary Dual-Bootstrap (CDUB) technique. Measured results indicate that the delay time is within 2.8 μs for the scan-line load modeling of TFT-LCD UXQA panel in a 5 V supply voltage. The obtained average power is 0.74 mW