An Improved BCH Code for Crossbar-Based Resistive RAM

Recently, the Error Correction Code(ECC) circuit has been applied to Resistive RAM(RRAM) that suffers from the process variations to improve the reliability and write power consumption. Furthermore, more high resistance state(HRS) cells in the array are beneficial for the crossbar-based RRAM to reduce the sneak current and operation power consumption. Therefore, this paper proposes an improved BCH code that the majority of RRAM cells are written to HRS. The weight distribution of the BCH code and the proposed one are obtained by Matlab. It indicates that the weight of the proposed BCH code(n, k-1) is less than n/2. In addition, the power/area/ latency overhead of all the encoder/decoder circuits are evaluated. Compared with the corresponding BCH encoders, the proposed BCH encoders exhibit higher area(average 6%) and higher latency(average 4.9%) with nearly the same power. As for the proposed decoder circuits, the power/area/latency overhead is almost the same as that of the corresponding BCH decoder circuits.Recently, the Error Correction Code(ECC) circuit has been applied to Resistive RAM(RRAM) that suffers from the process variations to improve the reliability and write power consumption. Furthermore, more high resistance state(HRS) cells in the array are beneficial for the crossbar-based RRAM to reduce the sneak current and operation power consumption. Therefore, this paper proposes an improved BCH code that the majority of RRAM cells are written to HRS. The weight distribution of the BCH code and the propoIEEE Beijing Section