A 16GS/s 6-bit Current-Steering DAC with TI topology in 40nm CMOS

A 6-bit pseudo segmented current-steering digital-to-analog converter(DAC) designed in 40 nm low-leakage(LL) CMOS process is presented. The DAC employs 4X time-interleaved(TI) topology which enables sampling rates up to 16GS/s with relatively low clock frequency. A design-for-test on-chip memory with 6bits1-k bytes/bit is programmed with strictly costumed data sequence and read out at 1Gb/s rate, independently. The DAC achieves 5.54-bit effective number of bit(ENOB) and 42.33 d Bc spurious free dynamic range(SFDR) at Nyquist frequency, respectively. Simulation results show the DAC consumes less than 230 mW power dissipation from 1.1V supply.A 6-bit pseudo segmented current-steering digital-to-analog converter(DAC) designed in 40 nm low-leakage(LL) CMOS process is presented. The DAC employs 4X time-interleaved(TI) topology which enables sampling rates up to 16GS/s with relatively low clock frequency. A design-for-test on-chip memory with 6bits1-k bytes/bit is programmed with strictly costumed data sequence and read out at 1Gb/s rate, independently. The DAC achieves 5.54-bit effective number of bit(ENOB) and 42.33 d Bc spurious free dynamic ranIEEE Beijing Section