Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective

With the rapid increase of leakage currents, non-volatile memories have become competitive candidates in the next-generation computer architecture. Among them, STT-MRAM shows great promise in working memory with high density, high speed and tremendous endurance, etc. However, based on our investigations, the dynamic write power and read reliability are two critical challenges of STT-MRAM. In this work, we propose a synergistic pseudo-differential sensing (PDS) framework that employs device, circuit and architectural techniques to address these challenges. In specific, three design techniques, including cell cluster, asymmetric sensing amplifier and self-error-detection-correction, are proposed to implement the PDS framework. We show that the holistic device-circuit-architecture cross-layer co-design enables STT-MRAM to be utilized in the cache memory, benefiting from the improved density, reliability and energy-efficiency. Our experimental results show that the proposed PDS scheme improves the read margin by similar to 35.6 percent, reduces the area, read latency, read energy, write latency and write power by similar to 46.7, similar to 9.8, similar to 30.3, similar to 2.3 and similar to 31.1 percent respectively, compared with the typical 1T1MTJ cell structure for the cache capacity of 8 MB. In addition, the proposed PDS scheme reduces the dynamic energy by similar to 32.9 percent and leakage energy by similar to 830 percent, improves the IPC by similar to 1.3 percent and miss rate by similar to 36.9 percent respectively, compared with conventional SRAM based cache.China Postdoctoral Science Foundation [2015M570024]; National Natural Science Foundation of China [61501013, 61571023]SCI(E)ARTICLE3531-5446