An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented.A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. the DNL/INL is 0.3/0.2LSB according to MATLAB simulation results.This ADC is implemented in ...An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented.A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. the DNL/INL is 0.3/0.2LSB according to MATLAB simulation results.This ADC is implemented in ...IEEE Beijing Section、Chinese Institute of Electronics (CIE)
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
The design techniques for analog-to-digital converters (ADCs) require careful optimization in order ...
In this paper, design and simulation results of an 8-bit 1 GS/s clock speed folding and interpolatin...
An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A...
This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC)...
This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converte...
A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A s...
A 8-bit 150MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-fol...
An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a...
Abstract — Analog to Digital converter plays an important role as the interface between analog and d...
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. T...
A CMOS analog to digital converter based on the folding and interpolating technique is presented. Th...
Abstract—An ADC using folding and interpolating tech-niques has been realised in 0.35 µm CMOS. A cur...
A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A s...
A CMOS analog to digital converter based on the folding and interpolating technique is presented. Th...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
The design techniques for analog-to-digital converters (ADCs) require careful optimization in order ...
In this paper, design and simulation results of an 8-bit 1 GS/s clock speed folding and interpolatin...
An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A...
This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC)...
This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converte...
A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A s...
A 8-bit 150MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-fol...
An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a...
Abstract — Analog to Digital converter plays an important role as the interface between analog and d...
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. T...
A CMOS analog to digital converter based on the folding and interpolating technique is presented. Th...
Abstract—An ADC using folding and interpolating tech-niques has been realised in 0.35 µm CMOS. A cur...
A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A s...
A CMOS analog to digital converter based on the folding and interpolating technique is presented. Th...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
The design techniques for analog-to-digital converters (ADCs) require careful optimization in order ...
In this paper, design and simulation results of an 8-bit 1 GS/s clock speed folding and interpolatin...