Add to ORKGInterconnection parasitic capacitance is the dominant delay and noise source in modern integrated circuits. This paper presents a test structure and a characterization method based on charge based capacitance measurement technique.The method could be implemented to study the variability of physic...Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated circuits. This paper presents a test structure and a characterization method based on charge based capacitance measurement technique.The method could be implemented to study the variability of physic...IEEE Beijing Section、Chinese Institute of Electronics (CIE)
[[abstract]]Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance meas...
This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts...
A method and a relative test structure for measuring the coupling capacitance between two interconne...
Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated cir...
[[abstract]]In this work, we describe a novel operation of charge-injection-induced error-free charg...
Geometry scaling increases the relative effect of coupling capacitances on performance, power, and n...
Interconnect parasitic parameters are the dominant source for delay and noise in modern integrated c...
The paper deals with a modified CBCM (Charge-Based Capacitance Measurements) method for nonlinear ca...
The measurement of capacitance by Charge Based Capacitor Measurement (CBCM) is the most widely used ...
[[abstract]]In this letter, charge-based capacitance measurement (CBCM) is applied to characterize b...
Charge-based capacitance measurements (CBCMs) are widely used to estimate on-chip wiring capacitance...
Abstract—In this paper, the on-wafer measurement of junction depletion capacitance is examined. This...
We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) th...
[[abstract]]Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance meas...
This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts...
A method and a relative test structure for measuring the coupling capacitance between two interconne...
Interconnection parasitic capacitance is the dominant delay and noise source in modem integrated cir...
[[abstract]]In this work, we describe a novel operation of charge-injection-induced error-free charg...
Geometry scaling increases the relative effect of coupling capacitances on performance, power, and n...
Interconnect parasitic parameters are the dominant source for delay and noise in modern integrated c...
The paper deals with a modified CBCM (Charge-Based Capacitance Measurements) method for nonlinear ca...
The measurement of capacitance by Charge Based Capacitor Measurement (CBCM) is the most widely used ...
[[abstract]]In this letter, charge-based capacitance measurement (CBCM) is applied to characterize b...
Charge-based capacitance measurements (CBCMs) are widely used to estimate on-chip wiring capacitance...
Abstract—In this paper, the on-wafer measurement of junction depletion capacitance is examined. This...
We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) th...
[[abstract]]Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance meas...
This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts...
A method and a relative test structure for measuring the coupling capacitance between two interconne...