High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture (CUDA), enables efficient description and implementation of independent computation cores. HLS tools can effectively translate the many threads of computation present in the parallel descriptions into independent, optimized cores. The generated hardware cores often heavily share input data and produce outputs independently. As the number of instantiated cores grows, the off-chip memory bandwidth may be insufficient to meet the demand. Hence, a scalable system architecture and a data-sharing mechanism become necessary for improving system performance. The network-on-chip (NoC) paradigm for intrachip communication has proved to be an e...
International audienceNetwork-on-Chip (NoC) is an interesting communicationfabric for multi processi...
Abstract With the increase in the number of cores embedded on a chip; The main challenge for Multip...
We can exploit the standardization of communication abstractions provided by modern high-level synth...
Data parallel languages such as CUDA and OpenCL efficiently describe many parallel threads of comput...
This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of i...
Recent progress in high-level synthesis (HLS) has helped raise the abstraction level of hardware des...
In this report, I will show that the current CUDA-to-FPGA (FCUDA) flow has been tested with a good s...
This thesis presents and evaluates a bus-based system for FCUDA, a translation tool enabling CUDA co...
The demand for high-performance computing has been growing significantly in the past decade. The bot...
Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and a...
This dissertation focuses on efficient generation of custom processors from high-level language desc...
International audienceIn this article, we present CuNoC, a new paradigm for intercom-munication betw...
Network-on-Chip (NoC) introduces parallelism in communications and emerges with the growing integrat...
Les réseaux sur puce (NoC pour «network on chip») sont des infrastructures de communication extensib...
As FPGA capacity increases, a growing challenge is connecting ever-more components with the current ...
International audienceNetwork-on-Chip (NoC) is an interesting communicationfabric for multi processi...
Abstract With the increase in the number of cores embedded on a chip; The main challenge for Multip...
We can exploit the standardization of communication abstractions provided by modern high-level synth...
Data parallel languages such as CUDA and OpenCL efficiently describe many parallel threads of comput...
This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of i...
Recent progress in high-level synthesis (HLS) has helped raise the abstraction level of hardware des...
In this report, I will show that the current CUDA-to-FPGA (FCUDA) flow has been tested with a good s...
This thesis presents and evaluates a bus-based system for FCUDA, a translation tool enabling CUDA co...
The demand for high-performance computing has been growing significantly in the past decade. The bot...
Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and a...
This dissertation focuses on efficient generation of custom processors from high-level language desc...
International audienceIn this article, we present CuNoC, a new paradigm for intercom-munication betw...
Network-on-Chip (NoC) introduces parallelism in communications and emerges with the growing integrat...
Les réseaux sur puce (NoC pour «network on chip») sont des infrastructures de communication extensib...
As FPGA capacity increases, a growing challenge is connecting ever-more components with the current ...
International audienceNetwork-on-Chip (NoC) is an interesting communicationfabric for multi processi...
Abstract With the increase in the number of cores embedded on a chip; The main challenge for Multip...
We can exploit the standardization of communication abstractions provided by modern high-level synth...