The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (Vgs= 0, Vds= Vdd) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that ...
International audienceThe single-event transient (SET) response of silicon-on-insulator (SOI) tri-ga...
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices...
Predictive compact models for two key variability sources in FinFET technology, the gate edge roughn...
The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is s...
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-...
Threshold voltage ðVT Þ and drive current ðIONÞ variability of low stand-by power (LSTP)-32 nm FinFE...
Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations ...
Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD too...
This paper developed a full three-dimensional (3-D) statistical simulation approach to investigate F...
FinFETs may start to replace planar MOSFETs for specific applications at the 32nm node and beyond du...
International audienceWe investigate Single-Event Transients (SET) in different designs of multiple-...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32nm Fin-FETs i...
none3noWhile traditional scaling used to be accompanied by an improvement in device performance, thi...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. ...
International audienceThe single-event transient (SET) response of silicon-on-insulator (SOI) tri-ga...
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices...
Predictive compact models for two key variability sources in FinFET technology, the gate edge roughn...
The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is s...
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-...
Threshold voltage ðVT Þ and drive current ðIONÞ variability of low stand-by power (LSTP)-32 nm FinFE...
Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations ...
Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD too...
This paper developed a full three-dimensional (3-D) statistical simulation approach to investigate F...
FinFETs may start to replace planar MOSFETs for specific applications at the 32nm node and beyond du...
International audienceWe investigate Single-Event Transients (SET) in different designs of multiple-...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32nm Fin-FETs i...
none3noWhile traditional scaling used to be accompanied by an improvement in device performance, thi...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. ...
International audienceThe single-event transient (SET) response of silicon-on-insulator (SOI) tri-ga...
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices...
Predictive compact models for two key variability sources in FinFET technology, the gate edge roughn...