Add to ORKGA new latched comparator architecture was proposed. Because of its very low kickback noise feature, it is especially suitable for differential analog-to-digital converters (ADCs). Simulated results of the proposed circuit in a 0.35 μm standard CMOS technology show that this comparator achieves a sampling speed of 400 Ms/s at 3.3-V supply, with a kickback noise 88% lower than conventional schemes.中文核心期刊要目总览(PKU)中国科技核心期刊(ISTIC)中国科学引文数据库(CSCD)5681-6844
Abstract — the fast growing electronics industry is pushing towards high speed low power analog to d...
Abstract — A new dynamic comparator is presented using modified gain stage followed by latch stage f...
This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full...
A new latched comparator architecture was proposed. Because of its very low kickback noise feature, ...
提出了一种新的闩锁型比较器结构.由于它的低kickback噪声特性,此比较器特别适合应用于差分模拟-数字转换器(ADCs).电路采用标准0.35 m的工艺进行模拟,结果显示此比较器在3.3V电源下采...
In this paper, A CMOS comparator with low power dissipation is presented. The preamplifier latch com...
Abstract--Dynamic comparators with high speed, low power and low offset voltage are the main prerequ...
A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital convert...
This study presents a fully differential dynamic comparator with low kickback noise, an effect cause...
Comparators are utilised by Nyquist-rate and oversampling analog to digital converters (ADCs) to acc...
Abstract—The need for extreme low power, efficient area and high speed ADC converters make use of th...
Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, p...
This paper deals with design methods and optimization techniques of dynamic latched comparators. It ...
ABSTRACT: A new double tail parallel latch load comparator are compared in term of voltage,power,del...
A high-speed low-power latched CMOS comparator circuit is presented. Demonstrated is a circuit optim...
Abstract — the fast growing electronics industry is pushing towards high speed low power analog to d...
Abstract — A new dynamic comparator is presented using modified gain stage followed by latch stage f...
This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full...
A new latched comparator architecture was proposed. Because of its very low kickback noise feature, ...
提出了一种新的闩锁型比较器结构.由于它的低kickback噪声特性,此比较器特别适合应用于差分模拟-数字转换器(ADCs).电路采用标准0.35 m的工艺进行模拟,结果显示此比较器在3.3V电源下采...
In this paper, A CMOS comparator with low power dissipation is presented. The preamplifier latch com...
Abstract--Dynamic comparators with high speed, low power and low offset voltage are the main prerequ...
A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital convert...
This study presents a fully differential dynamic comparator with low kickback noise, an effect cause...
Comparators are utilised by Nyquist-rate and oversampling analog to digital converters (ADCs) to acc...
Abstract—The need for extreme low power, efficient area and high speed ADC converters make use of th...
Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, p...
This paper deals with design methods and optimization techniques of dynamic latched comparators. It ...
ABSTRACT: A new double tail parallel latch load comparator are compared in term of voltage,power,del...
A high-speed low-power latched CMOS comparator circuit is presented. Demonstrated is a circuit optim...
Abstract — the fast growing electronics industry is pushing towards high speed low power analog to d...
Abstract — A new dynamic comparator is presented using modified gain stage followed by latch stage f...
This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full...