High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis

Image scaling is a fundamental algorithm used in a large range of digital image applications. In this paper, we propose an efficient VLSI architecture for a novel edge-directed linear interpolation algorithm. Our VLSI design is implemented using high level synthesis (HLS) tool, which generates RTL modules from C/C++ functions. HLS provides significantly improved design productivity compared to the traditional RTL-based design flow. So we explored a large design space including several fine-grained and coarse-grained optimizations in the pipeline architecture design. Our architecture is verified in a working system based on Xilinx Kintex-7 FPGA. Experiments show that our design can process UHD (3840* 2160) videos at 30fps with moderate resource utilization.EICPCI-S(ISTP)mmli@pku.edu.cn; pengzh@cs.ucla.edu; czhu@pku.edu.cn; hzjia@pku.edu.cn; donxie@pku.edu.cn; cong@cs.ucla.edu; wgao@pku.edu.cn92-9