A clock optimization method in the digital zooming of the image signal processing system

We address the problem of producing an enlarged picture from a given digital image (zooming). We propose a method that tries to take into account the difficulty to apply the very fast clock in the digital zooming unit of an ISP system. The ISP system hardware is realized in the FPGA and the zooming algorithm is parabola interpolation architecture. This paper presents an optimization method by using a synchronization FIFO to greatly reduce the clock frequency of the digital zooming unit, and by this the power consumption is also decreased significantly. ? (2014) Trans Tech Publications, Switzerland.EI