A 40-Gb/s low-power wireline transceiver architecture with multi-phase injection-locked clocking scheme

A low-power transceiver architecture that employs multi-phase injection-locked clocking scheme is presented. The minimal power consumption is realized by reducing global clock frequency and using the interleaving/multi- phase techniques. Besides, injection-locked clocking is utilized to prevent the degradation of transceiver jitter performance. In a 65-nm CMOS process, the proposed 40-Gb/s transceiver consumes 170 mW and achieves the power efficiency of 4.25 mW/Gb/s. ? 2012 IEEE.EI