An energy-efficient combining way selective technique for the instruction cache in superscalar microprocessors

Way selective technique could reduce the instruction cache energy consumption significantly. However, existing solutions usually bring extra fetch latency due to mispredictions or complicated updating mechanism, reducing the energy-efficiency. The paper presents an energy-efficient Combining Way Selective Cache for the instruction cache in superscalar processors (CWS-Cache). It combines the advantages of way prediction and way history techniques, and selects the best way selective mechanism for different situations. It not only reduces the instruction fetch energy effectively, but also improves performance by reducing the latency of misalignment fetch groups. Experimental results demonstrate that, on average, CWS-Cache reduces fetch energy consumption of the 8-way set-associative instruction cache in the baseline processor by 84.98%, and improves performance by 3.5%. Compared with three existing techniques, CWS-Cache improves the energy-delay product (EDP) by 15.48%, 14.13%, and 8.76%, respectively.EI0112473-24793