A bus arbitration scheme for memory access performance optimization

Memory access performance is strongly dependent on the processing sequence of memory transactions. On a system bus, the outstanding memory transactions issued by a bus device often have consecutive address and the same read or write (R/W) types. Under traditional bus arbitration schemes, however, outstanding transactions from different devices are most likely to be interleaved with each other, which incurs non-sequential addressing access as well as different R/W types access. Due to the limited scheduling performance of the memory controller, such sequences usually prevent the memory controller from accessing the memory effectively. In this paper, we propose a novel bus arbitration scheme, CGH, to minimize the number of memory row addressing and R/W type context switches. CGH can recognize and grant outstanding transaction sequence from the same bus device with the same row address and R/W type. It also prioritizes the requests which have the same memory row address and R/W type as the most recent transaction during grant handoff to achieve further improvement. Being applied to the PKUnity-SK SoC, the proposed arbitration scheme significantly elevates the memory access performance by 21.37% with only 2.83% area overhead. It also reduces the memory power consumption by 15.15% because of less row activations.EI051061-10714