A reconfigurable processor being suitable for multimedia

By using an array processor methodology, a reconfigurable processor ReMAP architecture was proposed, which is based on the single instruction multiple data. 2-dimensional discrete cosine transforms (2-D DCT) on the ReMAP prototype chip were implemented, the prototype chip on redesigning the multiple accumulator was optimized, adding the local registers and increasing the sharing registers among the processing element and transfer the data on different levels in the processing element. Based on the optimization, we proposed an optimized ReMAP architecture and verified it on field programming gate array. The result of implementing the 2D-DCT and sum of absolute differences shows that the optimized ReMAP architecture, comparing to the ReMAP prototype chip and other processors, obtains a higher performance speedup. ReMAP supported multiple arithmetic logic unit, and can full use of the inherent parallelism of the media algorithm. The scalable of ReMAP architecture can further improve the performance speedup to meet the media processing applications.EI0169-723