CMOS combinational circuit leakage power reduction using genetic algorithms

A leakage power reduction platform for CMOS combinational circuits by means of input vector control is presented. Genetic algorithm is used for searching minimum leakage vector and circuit status difference is used as fitness function. Experimental results show that this circuit status difference based genetic algorithm can achieve satisfied leakage power reduction, and runtime is reasonable. This method has no requirement for HSpice simulation and independent from target technology library.EI03421-4274