Add to ORKGIn this paper, we propose an on-demand mechanism for data cache leakage power management, which manages data cache activities according to the demand of memory accessing instructions. Specifically, this mechanism keeps the whole data array in leakage-saving mode whenever it finds no memory accessing instructions at all; once a load instruction is detected, it employs two data cache access control policies and the dynamic selection scheme to capture the access demand of the load address early in the pipeline. Experimental results demonstrate that the data cache leakage power is reduced by an average of 85.4%. Meanwhile, the performance is increased by 4.41%. Compared to traditional methods, the mechanism proposed in this paper achieves bette...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
本文提出面向访问需求的数据缓存泄漏功耗管理方法,根据访存指令对数据缓存的访问需求控制数据缓存的活动.当流水线中未发现访存指令时,将整个数据缓存保持在非活跃状态;而当发现访存指令进入流水线时,采用两种数...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
A number of techniques to reduce the cache leakage energy have so far been proposed. However, the lo...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
This paper proposes a combination of circuit and architectural techniques to maximize leakage power ...
Leakage energy optimization for caches has been the target of much recent effort. In this work, we f...
Energy management is important for a spectrum of systems ranging from high-performance architectures...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
本文提出面向访问需求的数据缓存泄漏功耗管理方法,根据访存指令对数据缓存的访问需求控制数据缓存的活动.当流水线中未发现访存指令时,将整个数据缓存保持在非活跃状态;而当发现访存指令进入流水线时,采用两种数...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
A number of techniques to reduce the cache leakage energy have so far been proposed. However, the lo...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
This paper proposes a combination of circuit and architectural techniques to maximize leakage power ...
Leakage energy optimization for caches has been the target of much recent effort. In this work, we f...
Energy management is important for a spectrum of systems ranging from high-performance architectures...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
本文提出面向访问需求的数据缓存泄漏功耗管理方法,根据访存指令对数据缓存的访问需求控制数据缓存的活动.当流水线中未发现访存指令时,将整个数据缓存保持在非活跃状态;而当发现访存指令进入流水线时,采用两种数...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...