Verification on Clock Domain Crossing (CDC) design is crucial to the SoC functional verification. Traditional model checking methods on CDC design do not consider the completeness of properties. However, generating complete design properties is the basis for model checking, and incomplete properties would lead to bug escape. To generate complete properties for CDC design, we first propose a finite state automaton based property generation method. Then, to solve the exponential explosive problem, we propose a metastability based data type reduction strategy. Experiment results on two typical CDC designs show that, our approach not only achieves 100% property coverage, but also discovers a bug that escaped by traditional methods. Meanwhile, t...
Abstract — A Modern complex SOC has a number of different asynchronous clock domains and data is fre...
Because of the difficulty of adequately simulating large digital designs, there has been a surge of ...
Verification of circuit description by means of model checking means to write propositions, expresse...
Traditional approach in RTL verification cannot completely verify the clock domain crossing (CDC) de...
International audienceWe propose a novel semi-automatic methodologyto formally verify clock-domain s...
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs ...
. An on-the-fly algorithm for model checking under fairness is presented. The algorithm utilizes sym...
Temporal logic model checking is one of the most widely used verification techniques. It allows to a...
The design of state-of-the-art digital circuits often involves interacting state machines with very ...
The clock distribution network is an essential component in every synchronous digital system. The de...
Coverage metrics for formal property verification (FPV) are gaining in significance as most chip des...
Counterexamples explain why a desired temporal logic property fails to hold. The generation of count...
This paper provides an overview on recently developed model generation techniques for SAT-based prop...
Contains fulltext : 34491.pdf (preprint version ) (Open Access
textIndustrial designs are becoming more complicated as technology advances and demand for higher p...
Abstract — A Modern complex SOC has a number of different asynchronous clock domains and data is fre...
Because of the difficulty of adequately simulating large digital designs, there has been a surge of ...
Verification of circuit description by means of model checking means to write propositions, expresse...
Traditional approach in RTL verification cannot completely verify the clock domain crossing (CDC) de...
International audienceWe propose a novel semi-automatic methodologyto formally verify clock-domain s...
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs ...
. An on-the-fly algorithm for model checking under fairness is presented. The algorithm utilizes sym...
Temporal logic model checking is one of the most widely used verification techniques. It allows to a...
The design of state-of-the-art digital circuits often involves interacting state machines with very ...
The clock distribution network is an essential component in every synchronous digital system. The de...
Coverage metrics for formal property verification (FPV) are gaining in significance as most chip des...
Counterexamples explain why a desired temporal logic property fails to hold. The generation of count...
This paper provides an overview on recently developed model generation techniques for SAT-based prop...
Contains fulltext : 34491.pdf (preprint version ) (Open Access
textIndustrial designs are becoming more complicated as technology advances and demand for higher p...
Abstract — A Modern complex SOC has a number of different asynchronous clock domains and data is fre...
Because of the difficulty of adequately simulating large digital designs, there has been a surge of ...
Verification of circuit description by means of model checking means to write propositions, expresse...