Shift-based hardware converter algorithm between binary and binary-coded decimal (BCD)

It appears many real-time applications with conversion delay between binary and decimal algorithms is a bottleneck of system performance. This paper introduces a kind of shift-based algorithm in order to shorten this delay with minimum cost. Based on the principle of data representation of binary and decimal algorithms, both binary-to-decimal and decimal-to-binary algorithms are deduced mathematically in equation. They are featured as converting data value through shift operation. Double of BCD, constructed to be Logic N, is atomic operation of binary-to-decimal bit-shifting conversion and half of BCD, constructed to be Logic M, is one of reverse conversion. Without carrying propagation froLogic M N to Logic N or froLogic M M to Logic M, the conversion speed only depends on the longest combinatorial path of Logic N or M. These radix-2r algorithms, i. e. by one-bit shift per cycle, is expanded to radix-2r algorithms, i.e. by multi-bit shift per cycle, to accelerate the conversion speed further. Finally, it shows that the shift-based algorithms are much faster than other algorithms by comparisons of these conversion algorithms.EI02221-2243