Add to ORKGThe degradation characteristics of both wide and narrow devices under Vg=Vd/2 stress mode are investigated. The width-enhanced device degradation can be seen with devices narrowing. The main degradation mechanism is interface state generation for pMOSFETs with different channel width. The cause of the width-enhanced device degradation is attributed to the combination of width-enhanced threshold voltage and series resistance.EI0121255-12602
The physical threshold voltage model of pMOSFETs under shallow trench isolation (STI) stress has bee...
This paper proposes a method which can separate the parasitic effect from the drain current I-d vs. ...
90 p.The purpose of this project is to study the gate oxide breakdown in ultra-thin pMOSFETs using c...
The effect of HALO dose on device parameter degradation of pMOSFET with 2.1 nm oxide and 0.135 ??m c...
Hot carrier stress degradation for short channel pMOSFETs with ultra-thin gate oxides (2.5 nm) and H...
Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress ...
Abstract- In this paper, we present new results on the width dependent hot-carrier (HC) degradation ...
Degradation of ultra-thin gate-oxide n-channel metal-oxide-semiconductor field-effect transistors wi...
The linear drain current degradation of n-MOSFETs with different channel lengths and gate oxide thic...
[[abstract]]The dependence of the performance of strained NMOSFETs on channel width was investigated...
Hot-Carrier degradation in p-channel MOSFET's is investigated comparing Hydrogen (H2) and Deuterium ...
\u3cp\u3eHot-carrier degradation is mainly caused by negative oxide-charge generation in the present...
Hot-carrier effects of p-MOSFETs with different oxide-thicknesses are studied in low gate voltage ra...
A detail experimental study on the reliability degradation of pMOSFET under non-uniform NBTI stress ...
Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET us...
The physical threshold voltage model of pMOSFETs under shallow trench isolation (STI) stress has bee...
This paper proposes a method which can separate the parasitic effect from the drain current I-d vs. ...
90 p.The purpose of this project is to study the gate oxide breakdown in ultra-thin pMOSFETs using c...
The effect of HALO dose on device parameter degradation of pMOSFET with 2.1 nm oxide and 0.135 ??m c...
Hot carrier stress degradation for short channel pMOSFETs with ultra-thin gate oxides (2.5 nm) and H...
Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress ...
Abstract- In this paper, we present new results on the width dependent hot-carrier (HC) degradation ...
Degradation of ultra-thin gate-oxide n-channel metal-oxide-semiconductor field-effect transistors wi...
The linear drain current degradation of n-MOSFETs with different channel lengths and gate oxide thic...
[[abstract]]The dependence of the performance of strained NMOSFETs on channel width was investigated...
Hot-Carrier degradation in p-channel MOSFET's is investigated comparing Hydrogen (H2) and Deuterium ...
\u3cp\u3eHot-carrier degradation is mainly caused by negative oxide-charge generation in the present...
Hot-carrier effects of p-MOSFETs with different oxide-thicknesses are studied in low gate voltage ra...
A detail experimental study on the reliability degradation of pMOSFET under non-uniform NBTI stress ...
Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET us...
The physical threshold voltage model of pMOSFETs under shallow trench isolation (STI) stress has bee...
This paper proposes a method which can separate the parasitic effect from the drain current I-d vs. ...
90 p.The purpose of this project is to study the gate oxide breakdown in ultra-thin pMOSFETs using c...