Design of data buffer circuit in high-speed, high-resolution video image acquisition system on FPGA

This paper introduces a logic circuit of data buffer between higher speed ADC and lower speed DSP. While allowing dropping some frames, the circuit also realizes effective image rescale and image buffer transfers frame by frame. The realization of this design initially solves the problem of the video capture system, which is limited by the resolution of the image, and enables DVR system to get high-speed access to large-resolution image.Computer Science, Artificial IntelligenceComputer Science, Information SystemsComputer Science, Software EngineeringComputer Science, Theory & MethodsEngineering, Electrical & ElectronicTelecommunicationsEICPCI-S(ISTP)