Sequential symbol synchronizers based on clock sampling by positive transitions

This work presents a sequential symbol synchronizer, that was discovered by us, and its functioning principle is based on the clock sampling by the input positive data transitions. This synchronizer has two topologies, namely the discrete and the continuous. Also, each topology has two versions which are the manual and the automatic. These synchronizers are very interesting, because the previous adjust of the manual version isn’t critical. The objective is to study the four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio)