A Low-Power dTLB Design Based on Memory Region Encoding

Translation lookaside buffers (TLBs) consume significant power due to their highly associative structure. This is getting worse with the increasing width of Virtual page number (VPN) and TLB capacity in 64-bit computing. In this paper, we present a new data TLB (dTLB) design that reduces VPN width to a large extent, thereby saving considerable power during TLB lookups. This design is motivated by an observation: the VPN can represent a much larger set of memory regions than what can be cached by the TLB at any time. We exploit this redundancy by encoding some high-order VPN bits with a shorter memory region id before the VPN is sent to dTLB. The consistency of the encoding and the recycling of memory region ids are taken cared by a small amount of hardware with little timing/power overhead. Experimental results on SPEC CPU2000 show a 37% energy reduction of dTLB with negligible performance penalty.Engineering, Electrical & ElectronicSCI(E)EI1ARTICLE4595-6011