A viable self-aligned bottom-gate MOSFET technology for high density and low voltage SRAM

This paper reports the implementation of the bottomgate MOSFET which possesses the following fully-selfaligned structural features: 1) self-aligned source/drain to bottom-gate; 2) self-aligned thick source/drain to thin channel; 3) self-aligned and mask-free lightly-dopeddrain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent CMP step. The process is applied to the poly-Si film, which is crystallized from an a-Si film deposited by LPCVD using Metal-Induced Uni-lateral Crystallization (MIUC) technique and is grain-enhanced further in a high temperature annealing step. Deep submicron Fully Self-Aligned Bottom-Gate (FSABG) PMOS transistors with channel length less than 0.5 ??m are fabricated. The measured performance parameters include threshold voltage of -0.43V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm2/V-s, off-current of 0.17 pA/??m and on-off current ration of 7.1??108.EI