Reconfigurable operators: New configuration logic blocks for novel FPGA

For current FPGA architectures, the fine-grain programmable blocks are the most flexible ones. However, they bring in massive configuration bits-stream and much performance loss. In this paper, we propose new configuration logic blocks for the latest FPGA, a collection of Reconfigurable Operators (ReOps). A ReOp is a basic block which can process multiple bits data with a specific function set. Considering the flexibility and regularity, we divide ReOps into seven groups, which are arithmetic ReOps, shift ReOps, bitwise logic ReOps, Multiplier ReOps, Register ReOps, Multiplexer ReOps and Memory ReOps. The function set of ReOps is roundness for the arbitrary ASIC (Application Specific Integrated Circuit) design. To build the development environment for this novel FPGA, we employ a new hardware design language and hardware compiler. To compare the performance between our work and other current FPGAs, we use configuration time and circuit delay as our evaluation measurements. And our experimental results show that our architecture achieves a great reduction on configuration bits-stream and comparable delay compared with Virtex5 FPGA. ? 2014 Binary Information PressEI0124153-41661