MCS-DMA: An optimization design of memory controller for DMA transfers in SoC

Current mainstream on-chip bus protocol - AHB has a problem that the bandwidth utilization of memory accesses is quite low. This paper proposes a new optimization design based on the feature that there are massive DMA transfers in SoC. Proposed method adds MCS-DMA modules inside the memory controller and bind MCS-DMA modules to target DMA transfers via software drivers. On the one hand, it prefetches data to increase the bandwidth utilization of single DMA transfer; on the other hand, it makes memory requests pipelined inside the memory controller, which increases the bandwidth utilization of multiple parallel DMA transfers. After applying the design to PKUnity-SK SoC, the bus bandwidth utilization when transferring single DMA increases to 100%. When transferring multiple DMAs in parallel, the bus bandwidth utilization increases from 33.3% to 85.5%. However, the chip area only increases by 2.9%.EI03598-6043