An adaptive edge enhancement algorithm and hardware implementation

In this paper, a novel adaptive edge enhancement algorithm is proposed. A noise reduction algorithm operated in 5??5 block on Y channel is also presented. With the parallel and pipelined structure, the processing time for a single pixel and an image is reduced efficiently. The hardware demo is designed and verified with Xilinx Virtex2 FPGA at frequency 90 MHz. ? 2010 IEEE.EI