Impacts of gate line edge roughness on sub 100nm MOSFETs

In this work, the effects of line edge roughness (LER) of nanometer scale gate pattern, 3 sigma standard deviation ranging from 9nm to 21nm, on MOSFET transistor performance fluctuations are investigated using three dimensional TCAD tools. Inhomogeneous source/drain (S/D) junction profile which is induced by gate LER through self-aligned S/D process is also taken into consideration. Hundreds of 60nm MOSFETs with gate line roughness are simulated in 3D by DESSIS device simulator to evaluate the effects of gate LER on device performance fluctuations. The simulation results reveal that gate pattern without appropriate control of LER may cause severe device performance variation, resulting in negative shift of average threshold voltage, sub-threshold slope degradation, and off state current exponential increase. Besides that, larger gate LER always results in boarder distribution of device characteristics. From simulation results, 3a standard deviation should be controlled below 9nm in order not to significantly degrade device performance and circuit reliability.EI