Design and test results of a readout circuit for high energy particle detectors

A readout integrated circuit for high energy particle detectors is presented. The circuit designed is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper with four selectable peaking time, and an output stage. The readout circuit has been designed in a 0.35um DPTM CMOS technology and tested with Verigy 93000. The size of readout circuit is 1.7*0.7mm 2. The power supply voltage is 5V. The average gain is about 20.5mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 550-650e for five chips in the typical mode. The power dissipation is about 8mW and 2mW respectively, with and without output buffer. The linearity reaches 99.2% in the typical mode. The gain is tunable from 13mV/fC to 130mV/fC and the peaking time varies from 700ns to 1.6us. ? 2009 SPIE.EI