Impacts of poly-si gate pre-implanted dopant on the performance and HCI reliability of 65nm nmos device

Poly-Si gate with pre-implanted dopant is found to minimize the effect of poly-depletion which is caused by ultra-thin gate oxides of the 0.1 um CMOS technology and below, however, high dose or high energy pre-implanted dopant has a potential impact on the performance of NMOS device. This work investigates the impacts of poly-Si gate pre-implanted dopant on the electrical performance, such as threshold voltage, saturation current and effective gate-oxide thickness, and HCI reliability test of 65nm NMOS device. Poly-depletion will be eliminated and the electrical performance of 65nm NMOS device will be improved by increasing dose and energy of doping, but the HCI reliability of device will degrade and serious scattering points issue will appear simultaneously. The electrical performance is mainly determined by the doping dose compared with energy, high doping energy will cause much more damage and the HCI reliability will degrade evidently. In order to get best performance of both electrical and reliability, high dose and low energy pre-implanted doping should be applied in 65nm CMOS application and below.EI