For the silicided GGnMOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, ballasting resistance is introduced to allow a more uniform current distribution. How the drain contact to gate spacing and contact to contact spacing influencing the ESD performance of the GGnMOS is investigated. We find that lengthening the contact to contact spacing can significantly improve the ESD performance of silicided GGnMOS. ? 2011 Springer-Verlag.EI
Electrostatic Discharge (ESD) is generally recognized as an increasingly important issue for modern ...
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[[abstract]]In the power management applications, the lateral double-diffusion MOS (LDMOS) transisto...
Gate-grounded NMOS (ggNMOS) transistors have widely served as electro-static discharge (ESD) protect...
In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious...
A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniform...
[[abstract]]With the rapid progress of electronic products, ESD (Electro-Static Discharge, ESD) is o...
Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripe...
Gate-grounded NMOS(gg NMOS) transistors have widely served as electro-static discharge(ESD)protectio...
This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS ...
New GGSCR Schottky-contact based to be adopted as ESD protection structure has been developed and an...
Ce travail de thèse vise à améliorer la méthodologie de modélisation du ggNMOS en régime de forts co...
A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-c...
A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-c...
International audienceA MOS-IGBT-SCR component that was proposed in a previous paper to increase the...
Electrostatic Discharge (ESD) is generally recognized as an increasingly important issue for modern ...
In the previous white paper, Selecting an Appropriate ESD Device, we focused solely on the idea that...
[[abstract]]In the power management applications, the lateral double-diffusion MOS (LDMOS) transisto...
Gate-grounded NMOS (ggNMOS) transistors have widely served as electro-static discharge (ESD) protect...
In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious...
A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniform...
[[abstract]]With the rapid progress of electronic products, ESD (Electro-Static Discharge, ESD) is o...
Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripe...
Gate-grounded NMOS(gg NMOS) transistors have widely served as electro-static discharge(ESD)protectio...
This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS ...
New GGSCR Schottky-contact based to be adopted as ESD protection structure has been developed and an...
Ce travail de thèse vise à améliorer la méthodologie de modélisation du ggNMOS en régime de forts co...
A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-c...
A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-c...
International audienceA MOS-IGBT-SCR component that was proposed in a previous paper to increase the...
Electrostatic Discharge (ESD) is generally recognized as an increasingly important issue for modern ...
In the previous white paper, Selecting an Appropriate ESD Device, we focused solely on the idea that...
[[abstract]]In the power management applications, the lateral double-diffusion MOS (LDMOS) transisto...