In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately. ? 2013 IEEE.EI
For the improvement of performance and noise tolerance in dynamic logic circuits, a technique is\ud ...
The need for low power dissipation in portable computing and wireless communication systems is makin...
In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given...
In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage S...
In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bul...
In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bul...
In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bul...
A variable threshold voltage keeper circuit technique using independent-gate FinFET technology is pr...
Abstract—In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over tradit...
Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short...
Abstract—In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over tradit...
Abstract—In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over tradit...
Scaling of single-gate bulk MOSFET faces great challenges in the nanometer regime due to the severe ...
Brute-force sequential circuits with reduced clock load and simpler circuitry are widely used in the...
A low-power manufacturable multi-threshold voltage (multi-V<sub>th</sub>) brute force latch based on...
For the improvement of performance and noise tolerance in dynamic logic circuits, a technique is\ud ...
The need for low power dissipation in portable computing and wireless communication systems is makin...
In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given...
In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage S...
In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bul...
In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bul...
In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bul...
A variable threshold voltage keeper circuit technique using independent-gate FinFET technology is pr...
Abstract—In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over tradit...
Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short...
Abstract—In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over tradit...
Abstract—In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over tradit...
Scaling of single-gate bulk MOSFET faces great challenges in the nanometer regime due to the severe ...
Brute-force sequential circuits with reduced clock load and simpler circuitry are widely used in the...
A low-power manufacturable multi-threshold voltage (multi-V<sub>th</sub>) brute force latch based on...
For the improvement of performance and noise tolerance in dynamic logic circuits, a technique is\ud ...
The need for low power dissipation in portable computing and wireless communication systems is makin...
In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given...