A cache coherence protocol is a vital component of a multiprocessor to maintain the data consistency. In this paper, we proposed VFCC, which is a simulation framework to validate a cache-coherence protocol implementation of a commercial 64-bit superscalar multiprocessor. It exploits multiple-level parallelism to accelerate validation without overheads among threads. Our experimental results demonstrate VFCC has a 5.0?? speedup than a traditional simulator on a conventional 16-core host machine. ? 2013 IEEE.EI
For power and performance reasons, multicores have become the dominant microprocessor architecture. ...
Although improved device technology has increased the performance of computer systems, fundamental h...
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of milli...
Multicore computing have presented many challenges for system designers; one of which is data consis...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
We describe a technique for verifying that a hardware design correctly implements a protocol. The ap...
In this research we built a SystemC Level-1 data cache system in a distributed shared memory archite...
: Virtual memory based cache coherence is a mechanism that relies only on hardware that already exi...
We present an analytical model of a cache coherent shared-memory multiprocessor and compare the resu...
International audienceThis paper presents a novel simulation-based approach which targets the perfor...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
This paper describes our experience applyingformal verification to the cache coherence protocol of t...
For power and performance reasons, multicores have become the dominant microprocessor architecture. ...
Although improved device technology has increased the performance of computer systems, fundamental h...
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of milli...
Multicore computing have presented many challenges for system designers; one of which is data consis...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
We describe a technique for verifying that a hardware design correctly implements a protocol. The ap...
In this research we built a SystemC Level-1 data cache system in a distributed shared memory archite...
: Virtual memory based cache coherence is a mechanism that relies only on hardware that already exi...
We present an analytical model of a cache coherent shared-memory multiprocessor and compare the resu...
International audienceThis paper presents a novel simulation-based approach which targets the perfor...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
This paper describes our experience applyingformal verification to the cache coherence protocol of t...
For power and performance reasons, multicores have become the dominant microprocessor architecture. ...
Although improved device technology has increased the performance of computer systems, fundamental h...
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of milli...