Novel electrostatic discharge protection design method

A novel ESD protection design method is proposed instead of the traditional experience-based trial-and-error electrostatic discharge (ESD) design approach. The new method resolves the costly and time-consuming problems of high-performance ESD protection development in sub/deep-sub micron CMOS technology. The method is conducted and verified in a 0.5 ??m CMOS process to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be greater than 5 kV.EI071156-11602