Static random access memory (SRAM) design based on adiabatic circuits

As a size of static random access memory (SRAM) design increases, the power also increases. This paper presents an SRAM design based on adiabatic circuits with all parts of the SRAM, including the decoder, cell, and sensor, designed with adiabatic circuits. A power model is presented for the SRAM design with various memory sizes simulated for various frequencies using 0.18 ??m 1.8 V CMOS technology. Experimental results show that the power of the adiabatic SRAM is substantially reduced. The power is reduced by more than 80% at 250 MHz.EI0101747-17504