Caches are widely used to reduce the speed gap between processors and memories. However, the spatial locality of sequential data accesses existing in many popular applications is not well exploited by conventional data cache. In response to these problems, the Split Sequential Data Cache (SSDC) is proposed, in which the sequential access detector can predict whether data accesses are sequential, and direct them to the right sub cache. Experiments show that the SSDC outperforms the conventional data cache and other schemes. It reduces the miss rate of applications with intensive sequential data accesses with only a little increment of bandwidth requirement. Meanwhile, the experimental results on SPEC2000Int show that SSDC does not hurt the p...
Treating data based on its location in memory has received much attention in recent years due to its...
In this paper we show that partitioning data cache into array and scalar caches can improve cache ac...
The purpose of this paper is to reevaluate the performance of the Split Temporal/Spatial (STS) cache...
Abstract Caches are widely used to reduce the speed gap between processors and memories. However, th...
During the last two decades, the performance of CPU has been developed much faster than that of memo...
The goal of cache design is to exploit data localities; however, the means to this end vary widely a...
Current split data caches classify data as having either spatial locality or temporal locality. The...
In recent years, CPU performance has become energy constrained. If performance is to continue increa...
Asymmetric-access caches with emerging technologies, such as STT-RAM and RRAM, have become very comp...
The performance of cache memories relies on the locality exhibited by programs. Traditionally this l...
The performance of superscalar processors is more sensitive to the memory system delay than their si...
International audienceAs the number of transistors on a chip doubles with every technology generatio...
The speed of processors increases much faster than the memory access time. This makes memory accesse...
This paper shows that even very small reconfigurable data caches, when split to serve data streams ...
The gap between processor speed and memory latency has led to the use of caches in the memory system...
Treating data based on its location in memory has received much attention in recent years due to its...
In this paper we show that partitioning data cache into array and scalar caches can improve cache ac...
The purpose of this paper is to reevaluate the performance of the Split Temporal/Spatial (STS) cache...
Abstract Caches are widely used to reduce the speed gap between processors and memories. However, th...
During the last two decades, the performance of CPU has been developed much faster than that of memo...
The goal of cache design is to exploit data localities; however, the means to this end vary widely a...
Current split data caches classify data as having either spatial locality or temporal locality. The...
In recent years, CPU performance has become energy constrained. If performance is to continue increa...
Asymmetric-access caches with emerging technologies, such as STT-RAM and RRAM, have become very comp...
The performance of cache memories relies on the locality exhibited by programs. Traditionally this l...
The performance of superscalar processors is more sensitive to the memory system delay than their si...
International audienceAs the number of transistors on a chip doubles with every technology generatio...
The speed of processors increases much faster than the memory access time. This makes memory accesse...
This paper shows that even very small reconfigurable data caches, when split to serve data streams ...
The gap between processor speed and memory latency has led to the use of caches in the memory system...
Treating data based on its location in memory has received much attention in recent years due to its...
In this paper we show that partitioning data cache into array and scalar caches can improve cache ac...
The purpose of this paper is to reevaluate the performance of the Split Temporal/Spatial (STS) cache...