Circuit design of a high performance CMOS continuous-time current comparator with gain boosting structures in parallel

In this paper, a novel high-accuracy and high-speed current comparator using gain boosting structures in parallel is proposed based on CSMC 0.5 mu m standard CMOS process. Two amplifiers are employed in the circuit whose open-loop gain has been fully used to improve the comparing accuracy. Simulation results reveal that a high resolution better than 0.01 mu A can be easily obtained by this approach. Some comparisons were made when amplifier open -loop gain retrogressed, power supply voltage scaled down or reference current varied. Detailed discussions about its average power dissipation and propagation delay are presented. The response delay is less than 16ns for +/- 0.1 mu A current difference at the supply voltage of 2V, which is expected to be further improved with 0.18 mu m standard CMOS process.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000245210600099&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, Electrical & ElectronicInstruments & InstrumentationPhysics, Condensed MatterCPCI-S(ISTP)