In this paper, the correlation between line-edge-roughness (LER) and line-width-roughness (LWR) is studied for the first time. Based on the characterization methodology of auto-correlation functions (ACF), a new theoretical model of LWR is proposed, in which the ACF of LWR can be analytically obtained from the ACFs of LER in the two line-edges. An improved method of generating "practical" lines with correlated LER is also proposed for statistical simulations. The model indicates that the LWR ACF is composed of two parts: one involves LER information, the other involves the cross-correlation of LER in the two line-edges, which agrees well with simulation results. It is also found that the correlation length of LWR reduces with incr...
Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-a...
LER/LWR performance is currently considered as one of the major stumbling blocks complicating progre...
Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution i...
In this paper,the correlation between line- edge-roughness(LER)and line-width-roughness (LWR)is stud...
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughn...
In this paper, the impacts of correlated line-edge roughness (LER) are investigated. Experimental st...
It has been widely recognized that variability is one the most important challenges to scaling of na...
Parameter uctuations found in ultrasmall devices are generally associated with discrete random dopan...
As the transistors are scaled down, undesirable performance mismatch in identically designed transis...
Abstract—The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transis...
Line edge roughness (LER) is a potential showstopper for the semiconductor industry. As the width of...
The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great poten...
In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gat...
The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistor...
Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing sc...
Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-a...
LER/LWR performance is currently considered as one of the major stumbling blocks complicating progre...
Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution i...
In this paper,the correlation between line- edge-roughness(LER)and line-width-roughness (LWR)is stud...
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughn...
In this paper, the impacts of correlated line-edge roughness (LER) are investigated. Experimental st...
It has been widely recognized that variability is one the most important challenges to scaling of na...
Parameter uctuations found in ultrasmall devices are generally associated with discrete random dopan...
As the transistors are scaled down, undesirable performance mismatch in identically designed transis...
Abstract—The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transis...
Line edge roughness (LER) is a potential showstopper for the semiconductor industry. As the width of...
The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great poten...
In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gat...
The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistor...
Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing sc...
Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-a...
LER/LWR performance is currently considered as one of the major stumbling blocks complicating progre...
Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution i...