Size Analysis of Multilevel RRAM Array and Optimization of Device and Circuit Characteristics

Multilevel RRAM array is one of the most promising candidates of next generation high density memory technology. In this paper, we investigate the size limitation of multilevel 1D1R RRAM array based on circuit simulation. Optimization of device characteristics and operation mode is obtained to increase the array size and the circuit performance. This work may be helpful for multilevel array design and application.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000319824700181&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, Electrical & ElectronicPhysics, AppliedCPCI-S(ISTP)