Microfabrication of Through Silicon Vias (TSV) for 3D SiP

A microfabrication flow for Through Silicon Via (TSV), as one of the critical and enabling technologies for three Dimensional System in Packaging (3D SiP), is presented in this paper. We focus on several critical processing steps for TSV fabrication, including: via micromachining; deposition of via insulation, barrier and Cu seed layer, Cu electroplating for via-fill. Si DRIE (Deep Reactive Ion Etching) methods are used for the microdrilling of vias. Copper electroplating techniques with Periodic Pulse Reverse (PPR) current and solutions made in-house, are investigated for the filling and metallization of vias. The initial results are demonstrated in this paper. Vias with diameter/space/depth of 40 pm (or plus)/100 mu m/100 mu m, have been successfully formed and filled, which proves the effectiveness of our efforts, and have partially paved the way to a multilayer-stacking homogeneous/heterogeneous integration-in-a package.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000265971001146&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, Electrical & ElectronicPhysics, AppliedEICPCI-S(ISTP)