Nowadays, H.264 is drawing more attention than other video coding standard because of greater compression ratio and higher video quality. This paper shows the implementation of H.264 on a Reconfigurable Multimedia Array Processor (ReMAP). Algorithm is realized by configuring the ALUs' operation and the communication relationship of the ALU array. ReMAP receives the dataflow, executes the operation with pipelined ALU elements as stream processor. Research shows that ReMAP can support realization of H.264 with comparable performance and achieve more flexibility.Engineering, Electrical & ElectronicNanoscience & NanotechnologyEICPCI-S(ISTP)
Video compression is a key technology used in several multimedia applications. Improvements in the c...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
The hardware performance of H.264 macroblock-parallel VBSME SAD structure is discussed, and a novel ...
By using an array processor methodology, a reconfigurable processor ReMAP architecture was proposed,...
Abstract The H.264/AVC video coding standard features diverse computational hot spots that need to b...
Current IC design, especially that for multimedia processing, requires high performance and short de...
Abstract—H.264/AVC is the latest video coding standard. It signifi-cantly outperforms the previous v...
In this paper, we present a high performance and low cost hardware architecture for real-time implem...
All Rights Reserved Video encoding has become an integral part for everyday computing from televisio...
In this paper, we present a high performance and low cost hardware architecture for real-time implem...
H.264 is a video coding standard which offers high data compression rate at the cost of a high compu...
This work is concerned about an H:264 CODEC implementation on FPGA. H.264 is a relative recent video...
In the context of Universal Multimedia Access, efficient techniques are needed for the adaptation of...
Nowadays, the television, movie and computer industry pose more strict requirements to what is a goo...
International audienceIn this paper, we present an implementation of an optimized H.264 intra 4 × 4 ...
Video compression is a key technology used in several multimedia applications. Improvements in the c...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
The hardware performance of H.264 macroblock-parallel VBSME SAD structure is discussed, and a novel ...
By using an array processor methodology, a reconfigurable processor ReMAP architecture was proposed,...
Abstract The H.264/AVC video coding standard features diverse computational hot spots that need to b...
Current IC design, especially that for multimedia processing, requires high performance and short de...
Abstract—H.264/AVC is the latest video coding standard. It signifi-cantly outperforms the previous v...
In this paper, we present a high performance and low cost hardware architecture for real-time implem...
All Rights Reserved Video encoding has become an integral part for everyday computing from televisio...
In this paper, we present a high performance and low cost hardware architecture for real-time implem...
H.264 is a video coding standard which offers high data compression rate at the cost of a high compu...
This work is concerned about an H:264 CODEC implementation on FPGA. H.264 is a relative recent video...
In the context of Universal Multimedia Access, efficient techniques are needed for the adaptation of...
Nowadays, the television, movie and computer industry pose more strict requirements to what is a goo...
International audienceIn this paper, we present an implementation of an optimized H.264 intra 4 × 4 ...
Video compression is a key technology used in several multimedia applications. Improvements in the c...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
The hardware performance of H.264 macroblock-parallel VBSME SAD structure is discussed, and a novel ...