研究了沟长从0.525μm到1.025μm 9nm厚的P-MOSFETs在关态应力(Vgs=0,Vds<0)下的热载流子效应.讨论了开态和关态应力.结果发现由于在漏端附近存在电荷注入,关态漏电流在较高的应力后会减小.但是低场应力后关态漏电流会增加,这是由于新生界面态的作用.结果还发现开态饱和电流和阈值电压在关态应力后变化很明显,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响.Idsat的退化可以用函数栅电流(Ig)乘以注入的栅氧化层电荷数(Qinj)的幂函数表达.最后给出了基于Idsat退化的寿命预测模型.The hot carrier effects under off-state stress mode (Vgs=0,Vds<0) have been investigated on 9nm P-MOSFETs with channel length varying from 1.025μm to 0.525μm.Both on-and off-state currents are discussed.It is found that the off-state leakage current decreases after a higher voltage stressing,which is induced by the charge injection occurred close to the drain junction.However,the leakage current increases after a lower voltage stressing because of the newly generated interface traps.It ...
This paper presents a method to measure the threshold voltage degradation Delta V-th along the chann...
本文提出了用线性余因子差分亚阈电压峰测量电应力诱生MOSFET界面陷阱的新技术并进行了实验验证.详细介绍了该方法的基本原理和实验实现,得到了电应力诱生MOSFET界面陷阱和累积应力时间的关系.该方法具...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
在最大衬底电流条件下(Vg=Vd/2),研究了不同氧化层厚度的表面沟道n-MOSFETs在热载流子应力下的退化.结果表明, Hu的寿命预测模型的两个关键参数m与n氧化层厚度有着密切关系.此外,和有着线...
研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面...
研究了不同沟道和栅氧化层厚度的n-MOS器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响.实验发现衬底正偏压对沟长1.135 μm,栅氧化层厚度2.5 n...
The hot carrier effects under off-state stress mode (Vgs=0, Vdsdsat can be expressed as a function o...
研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.国家重点基础研究...
Hot-carrier effects of p-MOSFETs with different oxide-thicknesses are studied in low gate voltage ra...
In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MO...
对氧化层厚度为4和5nm的n-MOSFETs进行了沟道热载流子应力加速寿命实验,研究了饱和漏电流在热载流子应力下的退化.在饱和漏电流退化特性的基础上提出了电子流量模型,此模型适用于氧化层厚度为4 5n...
DoctorThis thesis investigates the effect of dynamic stress (ON/OFF waveform) on reliability of nano...
Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under CHC/GIDL alternating stress is...
研究了在恒压应力下超薄栅nMOSFET软击穿后的衬底电流特性.软击穿时间由衬底电流随时间的弛豫特性和器件输出特性测量时监测的衬底电流突变确定.发现软击穿时间的威布尔斜率和衬底特征击穿电流随温度的升高而...
Nous étudions le vieillissement à 77 K de transistors MOS de type N soumis à de fortes contraintes é...
This paper presents a method to measure the threshold voltage degradation Delta V-th along the chann...
本文提出了用线性余因子差分亚阈电压峰测量电应力诱生MOSFET界面陷阱的新技术并进行了实验验证.详细介绍了该方法的基本原理和实验实现,得到了电应力诱生MOSFET界面陷阱和累积应力时间的关系.该方法具...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
在最大衬底电流条件下(Vg=Vd/2),研究了不同氧化层厚度的表面沟道n-MOSFETs在热载流子应力下的退化.结果表明, Hu的寿命预测模型的两个关键参数m与n氧化层厚度有着密切关系.此外,和有着线...
研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面...
研究了不同沟道和栅氧化层厚度的n-MOS器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响.实验发现衬底正偏压对沟长1.135 μm,栅氧化层厚度2.5 n...
The hot carrier effects under off-state stress mode (Vgs=0, Vdsdsat can be expressed as a function o...
研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.国家重点基础研究...
Hot-carrier effects of p-MOSFETs with different oxide-thicknesses are studied in low gate voltage ra...
In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MO...
对氧化层厚度为4和5nm的n-MOSFETs进行了沟道热载流子应力加速寿命实验,研究了饱和漏电流在热载流子应力下的退化.在饱和漏电流退化特性的基础上提出了电子流量模型,此模型适用于氧化层厚度为4 5n...
DoctorThis thesis investigates the effect of dynamic stress (ON/OFF waveform) on reliability of nano...
Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under CHC/GIDL alternating stress is...
研究了在恒压应力下超薄栅nMOSFET软击穿后的衬底电流特性.软击穿时间由衬底电流随时间的弛豫特性和器件输出特性测量时监测的衬底电流突变确定.发现软击穿时间的威布尔斜率和衬底特征击穿电流随温度的升高而...
Nous étudions le vieillissement à 77 K de transistors MOS de type N soumis à de fortes contraintes é...
This paper presents a method to measure the threshold voltage degradation Delta V-th along the chann...
本文提出了用线性余因子差分亚阈电压峰测量电应力诱生MOSFET界面陷阱的新技术并进行了实验验证.详细介绍了该方法的基本原理和实验实现,得到了电应力诱生MOSFET界面陷阱和累积应力时间的关系.该方法具...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...